1. Technical Field
The disclosure relates generally to the field of electronics devices, as well as networks thereof. More particularly, in one exemplary aspect, the disclosure is directed to methods and apparatus for implementing an inter-device (e.g., processor communication or IPC link between two (or more) independently operable devices. Various aspects of the present disclosure are directed to, inter alia, power management.
2. Description of Related Technology
Many electronic devices, such as e.g., mobile devices and portable computing devices, include integrated circuits such as e.g., an Application Processor (AP) system on a chip (SoC), which is a main processor chip designed to support one or more applications running in the operating environment of the electronic device (e.g., host processor). The AP is in data communication with other peripheral chipsets (e.g., processors) of the device, such as e.g., cellular and/or Wi-Fi chipsets via a memory-mapped interconnect and/or bus.
Various bus architectures and techniques have evolved over time which enable handling of increasingly faster data rates and provide higher levels of data throughput for the AP and/or peripheral processors. One such example is Peripheral Component Interconnect Express (PCIe); see e.g., PCI Express Base Specification Revision 3.1 dated Oct. 8, 2014. PCIe is a high-speed serial computer expansion bus standard designed to replace older PCI and similar bus standards. In terms of architecture, PCIe is based on point-to-point connectivity with separate serial links connecting each endpoint peripheral component (e.g., graphics card, memory, Wi-Fi, cellular, etc.) to the root complex or host processor (including the AP).
Communication between the AP and the peripheral chipsets via PCIe has many desirable attributes in terms of, inter alia, performance and flexibility. However, PCIe (as well as some other existing “computer-centric” bus technologies) suffer certain disabilities, especially from the standpoint of portable consumer electronic device implementations. Specifically, as noted above, extant PCIe technologies were developed for use within desktop, server, and laptop computers, which are to varying degrees agnostic to many electrical power considerations affecting smaller portable devices. Desktops and servers (and to a lesser degree laptops) are less concerned with electrical power consumption/conservation, and more concerned with bus performance, ability to “hot plug”, and the like. Accordingly, implementing a technology such as PCIe which, in its current incarnation, both (i) consumes significant electrical power during operation, and (ii) has limited power management infrastructure (e.g., application or host processor and chipset “sleep” states, and management of data and transactions during such sleep states), is generally unsuitable for portable consumer electronics applications where power consumption and battery conservation are critical (such as e.g., cellular- and Wi-Fi-enabled smartphones, tablets, “phablets”, portable media players, etc.). Further, other device components, such as the AP and the peripheral chipsets each consume additional electrical power during operation.
In order to limit power consumption within the electronic device, both of the AP and the peripheral chipsets may be automatically and independently switched between one or more lower power states (e.g., an awake-low power state, a sleep-low power state, etc.) during periods of non-use and a higher power state (e.g., an awake-high power state) during periods of use. There is generally a power consumption versus latency trade-off, where the lowest power state (e.g., sleep-low power) consumes the least amount of power but requires a longer duration of time to return to the fully awake state. Further, the energy cost associated with switching from the sleep-low power state to the fully awake state is potentially greater than that associated with switching from the awake-low power state to the fully awake state. Therefore it is typically desirable that the AP and/or the peripheral chipsets enter their lowest power states only during longer periods of non-use.
In some instances, user inactivity can initiate switching from a fully awake state to a lower power state. For example, after a shorter period of user inactivity, the AP may be switched to the awake-low power state, while after a longer period of user inactivity, the AP may be switched to the sleep-low power state. In other instances, activity or communication from the AP and the peripheral chipsets can initiate switching from a lower power state to a fully awake state (e.g., an awake-high power state) if the other chip is in a lower power state. For example, activity or communication from the AP, such as e.g., an uplink request, can initiate switching of the peripheral chipset in a lower power state to a fully awake state and/or activity or communication from the peripheral chipset, such as e.g., a downlink request, can initiate switching of the AP in a lower power state to a fully awake state. In the foregoing examples, mechanisms for causing switching and transition to a fully awake state may include built-in mechanisms from the interconnect (e.g., PCIe), such as e.g., PCIe WAKE# general purpose input/output (GPIO), or out-of-band mechanisms independent of the interconnect, such as e.g., a proprietary GPIO.
The interconnect (e.g., PCIe) between the AP and the peripheral chip sets may be controlled by a software layer, referred to as an inter-processor communication (IPC) layer. The IPC layer may define various power states to achieve different power versus latency tradeoffs. In some examples, the IPC layer may allow the AP to enter the lowest power state (e.g., sleep-low power), while in other examples the IPC layer may prevent the AP from entering the lowest power state. The peripheral chipset may signal the IPC layer to switch from a lower power state to a higher power state. Thus, signaling from the peripheral to the IPC layer may subsequently signal the AP to switch from a lower power state to a higher power state.
The AP may be responsible for initiating all uplink and downlink transactions. Thus, peripheral chipsets are only able to send a downlink data packet when the AP is in the awake-high power state and enables or opens the corresponding interconnect pathway (e.g., a “unidirectional pipe”). In a related aspect, the peripheral chipsets may signal to the AP to open an interconnect pathway, thereby requesting “wake up” (i.e., switching from a lower power state to a higher power state) of the AP if the AP is in a lower power state. In some cases, the peripheral chipset may continuously or repeatedly request “wake up” of the AP if there is no response from the AP and/or if there is an error in transfer of the data packet, thereby causing unnecessary power consumption by the peripheral chipset, the interconnect, and/or the AP. Such operational scenarios and requirements are quite common with the aforementioned cellular devices, media players, and similar devices.
Hence, there is a need for improved apparatus and associated methods which can leverage the high data throughput and other desirable attributes of bus technologies such as PCIe (and other “memory mapped” technologies), yet support the requirements of rigorous power management and conservation, as well as the ability to support various combinations of operational sleep states or other reduced-power modes by various chips or chipsets within the device.